Arithmetic frequency synthesizers, such as described in commonly assigned U.S. Pat. No. 4,766,560 of D. N. Curry et al., which issued December 23, 1985 on a "Parallel/Pipelined Arithmetic Variable Clock Frequency Synthesizer," are well suited for use as variable frequency bit clock generators for digital printing because they provide linear frequency control over a wide dynamic range. They characteristically include an accumulator for recursively accumulating an R-bit long binary input word having a time dependent value, N, at a preselected, stable reference frequency, F.sub.R, so the most significant bit (MSB) of the accumuland (i.e., the word accumulated by the accumulator) oscillates at a frequency, F.sub.BC (herein referred to as the "bit clock frequency") that is given for any value of N within the range -2.sup.R-1 .ltoreq.N&lt;2.sup.R-1 by: EQU F.sub.BC =F.sub.R (N/2.sup.R) (1)
U.S. Pat. No. 4,766,560 discloses a suitable implementation for such an arithmetic frequency synthesizer, so it is hereby incorporated by reference.
As is known, digital printing conventionally is carried out by providing a reflective, multi-faceted polygon which is rotated about its central axis to repeatedly scan one or more intensity modulated light beams across a photosensitive recording medium in a fast scan (i.e., line scan) direction while the recording medium is advancing in an orthogonal slow scan (i.e., process) direction, such that the beam or beams scan the recording medium in accordance with a raster scanning pattern. Each of the light beams is intensity modulated in accordance with a serial data sample stream at a rate determined by a bit clock frequency, whereby the individual picture element ("pixels") of the image represented by the data samples are printed on the recording medium in positions more or less precisely determined by the bit clock.
Digital printers ordinarily have start of scan detectors for resynchronizing their bit clocks at the beginning of each scan, thereby reducing pixel positioning errors caused by bit clock phase jitter. Thus, when an arithmetic frequency synthesizer is employed as a bit clock generator for such a printer, its accumulator typically is synchronously initialized from a zero or "cleared" state in response to a start of scan pulse at the start of each scan, thereby limiting the phase jitter of the bit clock, F.sub.BC, it generates to .+-. one half the period of the reference clock frequency, F.sub.R.
U.S. Pat. No. 4,766,560 teaches that the value N of the input word for the accumulator of such frequency synthesizer can be varied as a function of time for adjusting the bit clock frequency, F.sub.BC, as required to compensate for (1) variations in the angular velocity at which the polygon is rotated ("motor hunt errors"), (2) variations in the angular velocity at which different facets of the polygon sweep the incident light beam or beams across the recording medium ("polygon signature errors"), and/or (3) variations in the linear velocity at which the light beam or beams sweep across different segments of the scan lines ("scan non-lenearity errors"). Polygon signature errors and scan non-linearity errors essentially are time invariant for a given printer, while the motor hunt errors normally vary at low frequency.
The phase transitions of the bit clock generated by an arithmetic frequency synthesizer span an integer number of reference clock cycles. Unfortunately, however, unless the value N of the input word for the accumulator happens to be an integer power of two (i.e., N=2.sup.K, where K is an integer), the spacing of the bit clock phase transitions more or less periodically vary by .+-. one half the period of the reference clock frequency. Therefore, whenever the accumulator input word value, N, is not an integer power of two (i.e., N.noteq.2.sup.K), the duty cycle of the bit clock tends to vary periodically at a moderately high frequency. Improved techniques for performing scan non-linearity compensation and motor hunt compensation with arithmetic frequency synthesizer are described in concurrently field and commonly assigned U.S. patent applications of D. N. Curry entitled "Piecewise Spatial Linearization of Arithmetically Synthesized Bit Clocks for Flying Spot Scanners" filed Dec. 23, 1988 under Ser. No. 07/289,847 and "Arithmetically Computed Motor Hunt Compensation for Flying Spot Scanners" filed Dec. 22, 1988 under Ser. No. 07/288,501, now U.S. Pat. No. 4,893,136, respectively.
Periodic duty cycle variations of the bit clock, F.sub.BC, for a digital printer are troublesome because an ordinary observer is able to detect very small, spatially periodic imperfections in printed images. For example, when lines are printed parallel to the process direction at a high spatial frequency, an observer is likely to detect almost any minor variations in the duty cycle of those lines if the duty cycle variations are essentially aligned in the process direction from scan line-to-scan line. That, unfortunately, is precisely the alignment that tends to be caused by periodic variations in the duty cycle of a bit clock generated by an arithmetic frequency synthesizer.